42 search results - page 2 / 9 » On the Power Management of Simultaneous Multithreading Proce... |
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ISPASS
2005
IEEE
13 years 11 months ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
CPHYSICS
2010
13 years 2 months ago
2010
We present TFORM, the version of the symbolic manipulation system FORM that can make simultaneous use of several processors in a shared memory architecture. The implementation use...