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» On the testability of SDL specifications
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EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
13 years 9 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
COMPSAC
2002
IEEE
13 years 10 months ago
Expanding an Extended Finite State Machine to aid Testability
The problem of testing from an extended finite state machine (EFSM) is complicated by the presence of infeasible paths. This paper considers the problem of expanding an EFSM in o...
Robert M. Hierons, T.-H. Kim, Hasan Ural
CODES
1998
IEEE
13 years 9 months ago
Hardware/software co-design of an ATM network interface card: a case study
This paper discusses a case study, the co-design of an ATM Network Interface Card (NIC). The NIC is aimed to interface applications with the physical network line. It is composed ...
Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ah...
COMPSAC
2002
IEEE
13 years 10 months ago
From MSC and UML to SDL
UML and MSC are widely used by software practitioners. SDL is an ITU standard language for telecommunications software specification. It has a formal semantics, and is supported b...
Stephan Bourduas, Ferhat Khendek, Daniel Vincent
RSP
1999
IEEE
160views Control Systems» more  RSP 1999»
13 years 9 months ago
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
Oliver Bringmann, Wolfgang Rosenstiel, Annette Mut...