17 search results - page 2 / 4 » On wirelength estimations for row-based placement |
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
With the increasing size and sophistication of circuits and specifically in the presence of IP blocks, new wirelength estimation methods are needed in the design flow of large-sca...
ISPD
2007
ACM
13 years 7 months ago
2007
ACM
Traditionally, research in global placement has focused on relatively few simple metrics, such as pure wirelength or routability estimates. However, in the real world today, desig...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can ...
ICCD
2008
IEEE
13 years 12 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...