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DAC
2001
ACM
14 years 5 months ago
On-Chip Communication Architecture for OC-768 Network Processors
Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. R...
ANCS
2008
ACM
13 years 6 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
13 years 10 months ago
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
Radu Marculescu
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 9 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
INFOCOM
2007
IEEE
13 years 11 months ago
On the Extreme Parallelism Inside Next-Generation Network Processors
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
Lei Shi, Yue Zhang 0006, Jianming Yu, Bo Xu, Bin L...