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MASCOTS
2008
13 years 7 months ago
On the Stability of Best Effort Flow Control Mechanisms in On-Chip Architectures
In this paper we present a centralized flow control scheme in NoCs in the presence of both elastic and streaming flow traffic paradigms. We model the desired Best Effort (BE) sour...
Mohammad Sadegh Talebi, Ahmad Khonsari
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
13 years 11 months ago
High-level architecture exploration for MPEG4 encoder with custom parameters
Abstract - this paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted arc...
Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Yo...
SAMOS
2007
Springer
13 years 12 months ago
Communication Architecture Simulation on the Virtual Synchronization Framework
As multi-processor system-on-chip (MPSoC) has become an effective solution to ever-increasing design complexity of modern embedded systems, fast and accurate HW/SW cosimulation of...
Taewook Oh, Youngmin Yi, Soonhoi Ha
CODES
2003
IEEE
13 years 11 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
SLIP
2006
ACM
13 years 11 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...