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VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
14 years 5 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri
DATE
2003
IEEE
138views Hardware» more  DATE 2003»
13 years 10 months ago
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-H...
TAICPART
2010
IEEE
125views Education» more  TAICPART 2010»
13 years 3 months ago
Synthesis of On-Line Planning Tester for Non-deterministic EFSM Models
Marko Kääramees, Jüri Vain, Kullo R...
DFT
1998
IEEE
78views VLSI» more  DFT 1998»
13 years 9 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...