36 search results - page 2 / 8 » One-Level Cache Memory Design for Scalable SMT Architectures |
SC
1992
ACM
13 years 9 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. This paper is motivated by the desire to provide an efficient and scalable software cache implementation of OpenMP on multicore and manycore architectures in general, and...
EUROPAR
2005
Springer
13 years 10 months ago
2005
Springer
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...
CDES
2008
13 years 6 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...