Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
The scarcity and large fluctuations of link bandwidth in wireless networks have motivated the development of adaptive multimedia services in mobile communication networks, where i...