38 search results - page 1 / 8 » Optimal Transistor Tapering for High-Speed CMOS Circuits |
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
ISLPED
2000
ACM
13 years 9 months ago
2000
ACM
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ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technol...
ISLPED
1996
ACM
13 years 8 months ago
1996
ACM
The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Usin...
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...