Optimal Transistor Tapering for High-Speed CMOS Circuits

10 years 6 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FET network. Currently, in a long seriesconnected FET chain, the dimensions of the transistors are decreased from bottom transistor to the top transistor in a manner where the width of transistors is tapered linearly or exponentially. However, it has not been mathematically proved whether either of these tapering schemes yields optimal results in terms of minimization of switching delays of the network. In this paper, we rigorously analyze MOS circuits consisting of long FET chains under the widely used Elmore delay model and derive the optimality of transistor tapering by employing variational calculus. Specifically, we demonstrate that neither linear nor exponential tapering alone minimizes the discharge time of the FET chain. Instead, a composition of exponential and constant tapering actually optimizes the...
Li Ding 0002, Pinaki Mazumder
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where DATE
Authors Li Ding 0002, Pinaki Mazumder
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