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» Optimal fault-tolerant linear arrays
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SPAA
2000
ACM
13 years 9 months ago
Fault tolerant networks with small degree
In this paper, we study the design of fault tolerant networks for arrays and meshes by adding redundant nodes and edges. For a target graph G (linear array or mesh in this paper),...
Li Zhang
DFT
2003
IEEE
120views VLSI» more  DFT 2003»
13 years 10 months ago
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Che...
IOLTS
2009
IEEE
231views Hardware» more  IOLTS 2009»
13 years 11 months ago
Designing fault tolerant FSM by nano-PLA
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
Samary Baranov, Ilya Levin, Osnat Keren, Mark G. K...
APPML
2005
68views more  APPML 2005»
13 years 4 months ago
A note on edge fault tolerance with respect to hypercubes
In the previous studies on k-edge fault tolerance with respect to hypercubes Qn, matrices for generating linear k-EFT(Qn) graphs were used. Let EFTL(n, k) denote the set of matric...
Tung-Yang Ho, Ting-Yi Sung, Lih-Hsing Hsu