23 search results - page 2 / 5 » Optimal wire sizing and buffer insertion for low power and a... |
DAC
2003
ACM
14 years 6 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
DAC
2010
ACM
13 years 3 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
DAC
2004
ACM
13 years 9 months ago
2004
ACM
In this paper, we investigate the problem of repeater insertion for low power under a given timing budget. We propose a novel repeater insertion algorithm to compute the optimal r...