23 search results - page 5 / 5 » Optimal wire sizing and buffer insertion for low power and a... |
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
EMSOFT
2007
Springer
13 years 11 months ago
2007
Springer
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Embedded system optimization typically considers objectives such as cost, timing, buffer sizes and power consumption. Robustness criteria, i.e. sensitivity of the system to variat...