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FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
13 years 10 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
ICCAD
2008
IEEE
138views Hardware» more  ICCAD 2008»
14 years 2 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
Amit Agarwal, Jason Cong, Brian Tagiku
DAC
2003
ACM
13 years 11 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
13 years 11 months ago
Customized regular channel design in FPGAs
FPGAs are one of the essential components in platform-based embedded systems. Such systems are customized and applied only to a limited set of applications. Also some applications...
Elaheh Bozorgzadeh, Majid Sarrafzadeh
FCCM
2006
IEEE
111views VLSI» more  FCCM 2006»
13 years 12 months ago
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...
Robert Strzodka, Dominik Göddeke