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ICCAD
2008
IEEE

Fault tolerant placement and defect reconfiguration for nano-FPGAs

12 years 3 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve injecting spare resources. However, these methods use predetermined spare placement that is not optimized for each netlist. This is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for nano-FPGAs at the placement stage; fault tolerant placements are generated that are amenable to fast defect reconfiguration through replacement of defective logic elements with spares. We propose a simulatedannealing based placement algorithm that produces placements with the objective of maximizing the chances of successful recovery from faults in logic elements within the circuit’s timing constraints. In addition, our study of the fault reconfiguration problem shows it is NP-Complete, and we propose a fast scheme for achieving a good reconfiguration solution for a random or clustered ...
Amit Agarwal, Jason Cong, Brian Tagiku
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2008
Where ICCAD
Authors Amit Agarwal, Jason Cong, Brian Tagiku
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