96 search results - page 1 / 20 » Optimization of Combinational Logic Circuits Based on Compat... |
DAC
1993
ACM
13 years 9 months ago
1993
ACM
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
CSREAESA
2003
13 years 6 months ago
2003
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...