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CSREAESA
2003

Power Optimized Combinational Logic Design

10 years 11 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in switching activity has been obtained with marginal increase in circuit area and delay.
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu
Added 31 Oct 2010
Updated 31 Oct 2010
Type Conference
Year 2003
Where CSREAESA
Authors R. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
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