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» Optimized on-chip pipelining of memory-intensive computation...
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HPCA
2012
IEEE
12 years 26 days ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
DAC
2002
ACM
14 years 6 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
BMCBI
2010
86views more  BMCBI 2010»
13 years 5 months ago
An automatic method for identifying surface proteins in bacteria: SLEP
Background: Bacterial infections represent a global health challenge. The identification of novel antibacterial targets for both therapy and vaccination is needed on a constant ba...
Emanuela Giombini, Massimiliano Orsini, Danilo Car...