Power balanced pipelines

Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been a primary design objective, as it maximizes instruction throughput. Unfortunately, this causes significant energy inefficiency in processors, as each microarchitectural pipeline stage gets the same amount of time to complete, irrespective of its size or complexity. For poweroptimized processors, the inefficiency manifests itself as a significant imbalance in power consumption of different microarchitectural pipestages. In this paper, rather than balancing processor pipelines for delay, we propose the concept of power balanced pipelines – i.e., processor pipelines in which different delays are assigned to different microarchitectural pipestages to reduce the power disparity between the stages while guaranteeing the same processor frequency/performance. A specific implementation of the concept uses cycl...

• Type: Journal
• Year: 2012
• Where: HPCA
• Authors: John Sartori, Ben Ahrens, Rakesh Kumar
• Keywords: Distributed And Parallel Computing, HPCA 2012, Instruction Throughput, Pipeline Stages, Pipelined Processors