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» Optimizing Loop Performance for Clustered VLIW Architectures
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HPCA
2009
IEEE
14 years 5 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
MOBIHOC
2007
ACM
14 years 4 months ago
Bounds for the capacity of wireless multihop networks imposed by topology and demand
Existing work on the capacity of wireless networks predominantly considers homogeneous random networks with random work load. The most relevant bounds on the network capacity, e.g...
Alireza Keshavarz-Haddad, Rudolf H. Riedi
SC
2009
ACM
13 years 11 months ago
Robust workflows for science and engineering
Scientific workflow tools allow users to specify complex computational experiments and provide a good framework for robust science and engineering. Workflows consist of pipelines ...
David Abramson, Blair Bethwaite, Colin Enticott, S...
MOBIHOC
2007
ACM
14 years 4 months ago
Capacity scaling in delay tolerant networks with heterogeneous mobile nodes
We provide a general framework for the analysis of the capacity scaling properties in mobile ad-hoc networks with heterogeneous nodes and spatial inhomogeneities. Existing analyti...
Michele Garetto, Paolo Giaccone, Emilio Leonardi