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EUROMICRO
1998
IEEE
13 years 9 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 2 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
13 years 9 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
ICCAD
2000
IEEE
149views Hardware» more  ICCAD 2000»
13 years 9 months ago
Dynamic Response Time Optimization for SDF Graphs
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods ...
Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst
COMPUTING
2004
204views more  COMPUTING 2004»
13 years 5 months ago
Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
Robert Strzodka, Marc Droske, Martin Rumpf