22 search results - page 2 / 5 » Optimizing equivalence checking for behavioral synthesis |
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also expon...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
FSEN
2009
Springer
13 years 8 months ago
2009
Springer
This note aims at providing a concise and precise Travellers Guide, Phrase Book or Reference Manual to the timed automata modeling formalism introduced by Alur and Dill [7, 8]. The...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
PLDI
2009
ACM
13 years 11 months ago
2009
ACM
Translation validation is a technique for checking that, after an optimization has run, the input and output of the optimization are equivalent. Traditionally, translation validat...