22 search results - page 4 / 5 » Optimizing equivalence checking for behavioral synthesis |
DSD
2010
IEEE
13 years 3 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
JGO
2011
12 years 8 months ago
2011
Abstract In many problems from different disciplines such as engineering, physics, medicine, and biology, a series of experimental data is used in order to generate a model that ca...
TCAD
2008
13 years 5 months ago
2008
Detecting symmetries has many applications in logic synthesis that include, amongst other things, technology mapping, deciding equivalence of Boolean functions when the input corre...
TACAS
2005
Springer
13 years 10 months ago
2005
Springer
Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Althoug...