2048 search results - page 1 / 410 » Optimizing pipelines for power and performance |
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
HPCA
2012
IEEE
12 years 26 days ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
HPCA
1996
IEEE
13 years 9 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...