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» Optimizing the Memory Bandwidth with Loop Morphing
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ASAP
2004
IEEE
89views Hardware» more  ASAP 2004»
13 years 8 months ago
Optimizing the Memory Bandwidth with Loop Morphing
José Ignacio Gómez, Paul Marchal, Sv...
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
12 years 16 days ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
CODES
2004
IEEE
13 years 8 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...
IPPS
1996
IEEE
13 years 9 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 2 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou