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» PPM Reduction on Embedded Memories in System on Chip
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ETS
2007
IEEE
91views Hardware» more  ETS 2007»
13 years 11 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
ASPDAC
2008
ACM
135views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Block cache for embedded systems
On chip memories provide fast and energy efficient storage for code and data in comparison to caches or external memories. We present techniques and algorithms that allow for an au...
Dominic Hillenbrand, Jörg Henkel
EDCC
2008
Springer
13 years 6 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
13 years 9 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 8 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...