623 search results - page 2 / 125 » Packet Routing in Dynamically Changing Networks on Chip |
AHS
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
ASPLOS
2010
ACM
13 years 8 months ago
2010
ACM
We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelengthbased routing, where the route followed by a packe...
ICALP
1998
Springer
13 years 9 months ago
1998
Springer
Interval Routing Schemes (IRS for short) have been extensively investigated in the past years with special emphasis on shortest paths. Besides their theoretical interest, IRS have...
DAC
2006
ACM
13 years 10 months ago
2006
ACM
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...