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CODES
2003
IEEE
13 years 10 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 5 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
ICC
2007
IEEE
135views Communications» more  ICC 2007»
13 years 11 months ago
Traffic Analysis of Optical Networks Based on Wavelength Division Multiplexed Clockwork Routing
—A new network architecture for high-speed low-latency interconnects is introduced, based on a combination of optical wavelength division multiplexing and the automatic packet se...
Emilio Bravi, David Cotter
SC
2005
ACM
13 years 11 months ago
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems
The interconnect plays a key role in both the cost and performance of large-scale HPC systems. The cost of future high-bandwidth electronic interconnects is expected to increase d...
Kevin J. Barker, Alan F. Benner, Raymond R. Hoare,...
ESTIMEDIA
2007
Springer
13 years 11 months ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes t...
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc...