Sciweavers

29 search results - page 6 / 6
» Parallel FFT Algorithms on Network-on-Chips
Sort
View
CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 5 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
IPPS
2010
IEEE
13 years 3 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
CPHYSICS
2004
92views more  CPHYSICS 2004»
13 years 5 months ago
Ultrahigh resolution simulations of mode converted ion cyclotron waves and lower hybrid waves
Full Wave studies of mode conversion (MC) processes in toroidal plasmas have required prohibitive amount of computer resources in the past because of the disparate spatial scales ...
J. C. Wright, P. T. Bonoli, E. D'Azevedo, M. Bramb...
PPL
2008
185views more  PPL 2008»
13 years 5 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...