38 search results - page 7 / 8 » Parallel Tiled QR Factorization for Multicore Architectures |
ISPAN
2005
IEEE
13 years 11 months ago
2005
IEEE
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
ASPLOS
2010
ACM
14 years 1 months ago
2010
ACM
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
ISBI
2008
IEEE
14 years 6 months ago
2008
IEEE
We present a novel use of GPUs (Graphics Processing Units) for the analysis of histopathologicalimages of neuroblastoma, a childhood cancer. Thanks to the advent of modern microsc...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...