8 search results - page 2 / 2 » Parallel and Fault-Tolerant Routing in Nanoscale Spin-Wave A... |
ICN
2005
Springer
13 years 11 months ago
2005
Springer
It is shown that the de Bruijn graph (dBG) can be used as an architecture for interconnection networks and a suitable structure for parallel computation. Recent works have classiï¬...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
ASAP
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...