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» Parallel fault backtracing for calculation of fault coverage
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PDP
2011
IEEE
12 years 9 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
SAFECOMP
2010
Springer
13 years 4 months ago
Reliability Analysis of Safety-Related Communication Architectures
Abstract. In this paper we describe a novel concept for reliability analysis of communication architectures in safety-critical systems. This concept has been motivated by applicati...
Oliver Schulz, Jan Peleska
IEEEPACT
2006
IEEE
13 years 11 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ASPLOS
2006
ACM
13 years 11 months ago
Ultra low-cost defect protection for microprocessor pipelines
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
Smitha Shyam, Kypros Constantinides, Sujay Phadke,...