53 search results - page 11 / 11 » Parallel programming and code selection in fortress |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
SASP
2008
IEEE
13 years 11 months ago
2008
IEEE
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
ASPLOS
1989
ACM
13 years 9 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...