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ICPR
2004
IEEE
14 years 5 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
DSN
2009
IEEE
13 years 8 months ago
Processor reliability enhancement through compiler-directed register file peak temperature reduction
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...
Chengmo Yang, Alex Orailoglu
HPCA
2000
IEEE
13 years 9 months ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
ICS
2007
Tsinghua U.
13 years 11 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
13 years 9 months ago
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
Radhika Thekkath, Susan J. Eggers