14 search results - page 1 / 3 » Parallel-pipelined architecture for 2-D ICT VLSI implementat... |
ICIP
2003
IEEE
14 years 6 months ago
2003
IEEE
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
TSP
2008
13 years 4 months ago
2008
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
ICIP
1994
IEEE
14 years 6 months ago
1994
IEEE
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
IJCNN
2000
IEEE
13 years 9 months ago
2000
IEEE
Selectiveattentionis a mechanismsused to sequentiallyselectthe spatiallocationsof salientregionsin the sensor’sfieldof view. This mechanism overcomesthe problem of flooding limi...
ICIP
1999
IEEE
14 years 6 months ago
1999
IEEE
In this paper, we present a VLSI architecture for separable 2-D Discrete Wavelet Transform (DWT). Based on 1-D DWT Recursive Pyramid Algorithm (RPA), a complete 2-D DWT output sch...