3 search results - page 1 / 1 » Parallelism-Aware Batch Scheduling: Enhancing both Performan... |
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
INFOCOM
1998
IEEE
13 years 9 months ago
1998
IEEE
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...