22 search results - page 2 / 5 » Parallelization of loops with exits on pipelined architectur... |
CGO
2008
IEEE
13 years 12 months ago
2008
IEEE
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
PLDI
2005
ACM
13 years 11 months ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
MICRO
1991
IEEE
13 years 9 months ago
1991
IEEE
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
ISHPC
2000
Springer
13 years 9 months ago
2000
Springer
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
This paper focuses on generating efficient software pipelined schedules for in-order machines, which we call Converged Trace Schedules. For a candidate loop, we form a string of t...