22 search results - page 5 / 5 » Parallelization of loops with exits on pipelined architectur... |
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
EUROGRAPHICS
2010
Eurographics
14 years 1 months ago
2010
Eurographics
We present a novel approach to ray tracing execution on commodity graphics hardware using CUDA. We decompose
a standard ray tracing algorithm into several data-parallel stages tha...