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DSN
2011
IEEE
12 years 4 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
COCO
2003
Springer
118views Algorithms» more  COCO 2003»
13 years 10 months ago
Lower bounds for predecessor searching in the cell probe model
We consider a fundamental problem in data structures, static predecessor searching: Given a subset S of size n from the universe [m], store S so that queries of the form “What i...
Pranab Sen
PARA
2000
Springer
13 years 8 months ago
JavaGrande - High Performance Computing with Java
The JavaGrande Forum is a group of users, researchers, and interested parties from industry. The Forum members are either trying to use Java for resource-intensive applications or ...
Michael Philippsen, Ronald F. Boisvert, Vladimir G...
3DIC
2009
IEEE
263views Hardware» more  3DIC 2009»
13 years 8 months ago
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwa...
EUROPAR
2004
Springer
13 years 10 months ago
Large-Scale Deployment in P2P Experiments Using the JXTA Distributed Framework
The interesting properties of P2P systems (high availability despite peer volatility, support for heterogeneous architectures, high scalability, etc.) make them attractive for dist...
Gabriel Antoniu, Luc Bougé, Mathieu Jan, S&...
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