356 search results - page 1 / 72 » Parallelizing time with polynomial circuits |
SPAA
2005
ACM
13 years 10 months ago
2005
ACM
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
DM
2002
13 years 4 months ago
2002
A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual grap...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
FOCS
2000
IEEE
13 years 9 months ago
2000
IEEE
We give new bounds on the circuit complexity of the quantum Fourier transform (QFT). We give an upper bound of Ç´ÐÓ Ò · ÐÓ ÐÓ ´½ µµ on the circuit depth for computin...