14 search results - page 2 / 3 » Parametric analysis to determine accurate interconnect extra... |
Publication
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitiviti...
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of su...