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» Part III: routers with very small buffers
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ANCS
2009
ACM
13 years 3 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
CCR
2006
110views more  CCR 2006»
13 years 5 months ago
Estimating network proximity and latency
Network proximity and latency estimation is an important component in discovering and locating services and applications. With the growing number of services and service providers...
Puneet Sharma, Zhichen Xu, Sujata Banerjee, Sung-J...
VLDB
2002
ACM
108views Database» more  VLDB 2002»
13 years 5 months ago
Generic Database Cost Models for Hierarchical Memory Systems
Accurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in ...
Stefan Manegold, Peter A. Boncz, Martin L. Kersten
SPAA
2009
ACM
14 years 2 months ago
A randomized, o(log w)-depth 2 smoothing network
A K-smoothing network is a distributed, low-contention data structure where tokens arrive arbitrarily on w input wires and reach w output wires via their completely asynchronous p...
Marios Mavronicolas, Thomas Sauerwald
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
13 years 10 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta