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ANCS
2009
ACM

Design and performance analysis of a DRAM-based statistics counter array architecture

10 years 11 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable research attention in recent years. This problem arises in a variety of router management and data streaming applications where large arrays of counters are used to track various network statistics and implement various counting sketches. It proves too costly to store such large counter arrays entirely in SRAM while DRAM is viewed as too slow for providing wirespeed updates at such high speeds. In this paper, we propose a DRAM-based counter architecture that can effectively maintain wirespeed updates to large counter arrays. The proposed approach is based on the observation that modern commodity DRAM architectures, driven by aggressive performance roadmaps for consumer applications (e.g. video games), have advanced architecture features that can be exploited to make a DRAM-based solution practical. In particula...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim
Added 16 Feb 2011
Updated 16 Feb 2011
Type Journal
Year 2009
Where ANCS
Authors Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim) Xu
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