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» Partial Product Reduction Based on Look-Up Tables
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ARITH
2007
IEEE
14 years 4 days ago
A New Family of High.Performance Parallel Decimal Multipliers
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
Álvaro Vázquez, Elisardo Antelo, Pao...
ICFP
2002
ACM
14 years 5 months ago
A compiled implementation of strong reduction
Motivated by applications to proof assistants based on dependent types, we develop and prove correct a strong reducer and equivalence checker for the -calculus with products, sums...
Benjamin Grégoire, Xavier Leroy
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 5 days ago
Power optimization of weighted bit-product summation tree for elementary function generator
— In this paper we propose a method for lowering the power consumption in our previously proposed method for approximating elementary functions. By rearranging the interconnect o...
Saeeid Tahmasbi Oskuii, Kenny Johansson, Oscar Gus...
CSREAESA
2003
13 years 7 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ARITH
1997
IEEE
13 years 10 months ago
Theory and applications for a double-base number system
In this paper we present a rigorous theoretical analysis of the main properties of a double base number system, using bases 2 and 3; in particular we emphasize the sparseness of t...
Vassil S. Dimitrov, Graham A. Jullien, William C. ...