58 search results - page 2 / 12 » Partial and Dynamically Reconfiguration of Xilinx Virtex-II ... |
AHS
2006
IEEE
13 years 11 months ago
2006
IEEE
Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic sy...
FPT
2005
IEEE
13 years 11 months ago
2005
IEEE
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
ARC
2007
Springer
13 years 9 months ago
2007
Springer
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
ERSA
2006
13 years 6 months ago
2006
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
JUCS
2007
13 years 5 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...