8 search results - page 1 / 2 » Partial scan designs without using a separate scan clock |
VTS
1995
IEEE
13 years 8 months ago
1995
IEEE
TCAD
1998
13 years 4 months ago
1998
Conventional scan design imposes considerable area and delay overhead by using larger scan
ip-
ops and additional scan wires without utilizing the functionality of the combinatio...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...