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ARC
2007
Springer
120views Hardware» more  ARC 2007»
13 years 9 months ago
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
ARCS
2006
Springer
13 years 8 months ago
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial...
Christopher Claus, Florian Helmut Müller, Wal...
IPPS
2007
IEEE
13 years 11 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
FPT
2005
IEEE
98views Hardware» more  FPT 2005»
13 years 10 months ago
Secure Partial Reconfiguration of FPGAs
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
Amir Sheikh Zeineddini, Kris Gaj
AHS
2006
IEEE
125views Hardware» more  AHS 2006»
13 years 11 months ago
Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs
Randomly connecting networks have proven to be universal computing machines. By interconnecting a set of nodes in a random way one can model very complicated non-linear dynamic sy...
Andres Upegui, Eduardo Sanchez