7 search results - page 2 / 2 » Passive Hierarchical Model Order Reduction and Realization o... |
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...