19 search results - page 4 / 4 » Path Delay Test Generation for Domino Logic Circuits in the ... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...
DAC
1994
ACM
13 years 9 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...