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Publication
266views
12 years 10 months ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...
ERSA
2006
197views Hardware» more  ERSA 2006»
13 years 6 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
CAMP
2000
IEEE
13 years 9 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
MM
1995
ACM
139views Multimedia» more  MM 1995»
13 years 8 months ago
A Feature-Based Algorithm for Detecting and Classifying Scene Breaks
We describe a new approach to the detection and classication of scene breaks in video sequences. Our method can detect and classify a variety of scene breaks, including cuts, fade...
Ramin Zabih, Justin Miller, Kevin Mai
ICIP
2006
IEEE
14 years 6 months ago
Hierarchical Data Structure for Real-Time Background Subtraction
This paper seeks to increase the efficiency of background subtraction algorithms for motion detection. Our method uses a quadtree-base hierarchical framework that samples a small ...
Johnny Park, Amy Tabb, Avinash C. Kak